_CPUID, CPUIDD & _CPUID$ Functions
Purpose
Global variables which return information about the processor.
Syntax
a = _CPUID
a = _CPUIDD
c$ = _CPUID$
a | : large variable |
c$ | : string variable |
Description
Each of these functions return specific information from internal registers, _CPUID returning Highest Function Parameter and Manufacturer ID information, _CPUIDD Processor Info and Feature Bits, while _CPUID$ returns the type of the processor.
An example of information that can be extracted from _CPUID: Show
The 14 lowest bits of _CPUID return the CPU type. The following is true:
_CPUID %& 0x3000
0 | Normal CPU |
1 | Overdrive CPU |
2 | Dual processor |
3 | Intel Reserved |
_CPUID %& 0x0fff
300 | |
300 | 386 (no CPUID-assembler instruction) |
4XX |
400 | 486 (no Cpuid-assembler instruction) |
44x | 486SL |
47x | 486DX2, WriteBack Enhanced |
48x | 486DX4 (or Overdrive) |
5XX |
51x | Pentium 60 or 66 (or Overdrive) |
52x | Pentium 75, 90, 100, 120, 133, 150, 166 or 200 (or Overdrive) |
53x | Pentium Overdrive 486 |
54x | Pentium MMX 166/200 |
54x | Pentium MMX Overdrive 75/90/100/120/133 |
6XX |
61x | Pentium Pro |
63x | Pentium II, Model 3 |
63x | Pentium II Overdrive |
65x | Pentium II-5, Celeron-5, Pentium II-Xeon |
66x | Celeron-6 |
67x | Pentium III, Pentium III-Xeon |
The Pentium II, Model 5, and the Celerons, or Pentium II-Xeon can be separated by the 2nd Level Cache Information. The same is true for Pentium III and Pentium III-Xeon.
For more up to date processor details, follow this link.
An exmaple of information that can be extracted from _CPUIDD: Show
Remarks:Since the Pentium III processor each has its own ID. The name and description of the _CPUIDD bits for Intel processors until Pentium III.
Bit | Name | Description |
0 | FPU | Floating-point unit on-chip - The processor contains an FPU that supports the Intel 387 floating-point instruction set. If Btst(_CPUIDD, 0) Then Print "FPU available" |
1 | VME | Virtual Mode Extension - The processor supports extensions to virtual-8086 mode. |
2 | DE | Debugging Extension - The processor supports I/O breakpoints, including the CR4.DE bit for enabling debug extensions and optional trapping of access to the DR4 and DR5 registers. |
3 | PSE | Page Size Extension - The processor supports 4-Mbyte pages. |
4 | TSC | Time Stamp Counter - The RDTSC instruction is supported including the CR4.TSD bit for access/privilege Control. If Btst(_CPUIDD, 4) Then _RDTSC possible. |
5 | MSR | Model Specific Registers - Model Specific Registers are implemented with the RDMSR, WRMSR instructions |
6 | PAE | Physical Address Extension |
7 | MCE | Machine Check Exception, Exception 18, and the CR4.MCE enable bit are supported |
8 | CX8 | CMPXCHG8 Instruction Supported |
9 | APIC | On-chip APIC Hardware Supported |
10 | | Reserved |
11 | SEP | Fast System Call Indicates whether the processor supports the Fast System Call instructions, SYSENTER and SYSEXIT. (Erratum in Pentium Pro, needs to examine _CPUID (Family 6, Model < 3, Stepping < 3: Not supported) |
12 | MTRR | Memory Type Range Registers supported (MTRR_CAP) |
13 | PGE | Page Global Enable - The global bit in the PDEs and PTEs and the CR4.PGE enable bit are supported. |
14 | MCA | Machine Check Architecture supported, specifically the MCG_CAP register. |
15 | CMOV | The processor supports CMOVcc, and if the FPU feature flag (bit 0) is also set, supports the FCMOVCC and FCOMI instructions. Pentium II+ and many Pentium Pro support somewhat faster Min and Max operations. |
16 | PAT | Page Attribute Table - Indicates whether the processor supports the Page Attribute Table. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory on a 4K granularity through a linear address. |
17 | PSE-36 | 36-bit Page Size Extension - Indicates whether the processor supports 4-Mbyte pages that are capable of addressing physical memory beyond 4GB. This feature indicates that the upper four bits of the physical address of the 4-Mbyte page is encoded by bits 13-16 of the page directory entry. |
18 | | Processor serial number is present and enabled. The processor supports the 96-bit processor serial number. feature, and the feature is enabled. |
19 | | CLFLUSH instruction (SSE2) |
20 | | Reserved |
21 | | Debug Store: save trace of executed jumps enabled |
22 | | Onboard thermal control MSRs for ACPI |
23 | | Intel Architecture MMX Technology supported If Btst(_CPUIDD, 23) or If IsMMX |
24 | FXSR | Fast floating point save and restore - Indicates whether the processor supports the FXSAVE and FXRSTOR instructions for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it uses the fast save/restore instructions. |
25 | | Streaming SIMD Extensions supported (Pentium III+) (3D-Katmai command) |
26 | | SSE2 instructions supported |
27 | | CPU cache implements self-snoop |
28 | | Hyperthreading supported and enabled |
29 | | Thermal monitor automatically limits temperature |
30 | | IA64 processor emulating x86 |
30 | | Pending Break Enable (PBE# pin) wakeup capability |
The processor serial number for Pentium III processors can be obtained using Btst(_CPUIDD, 18) or _CPUID 3 in HEX in _CPUID and _ECX and _EDX (according Intel to show as 6 times 4 Hex characters in uppercase).
For more details of the type of information returned see here.
Example
OpenW 1
Print _CPUID$ // Returns the type of processor
Print Btst(_CPUIDD, 0) // True if the processor contains a FPU (should always be TRUE these days)
Print (_CPUID And $3000) // Returns CPU type (usually 0 - Normal CPU)
Print (_CPUID And $0FFF) // Returns the CPU type
Do : Sleep : Until Me Is Nothing
Remarks
The global variables _CPUID$, _CPUID, and _CPUIDD are initialized at startup. The compiler does not generate a cpuid assembler instruction, but instead generates code to read these global variables. To initialize these global variables the cpuid instruction is invoked with different 'input parameters'. To obtain specific information from the CPU the eax register must be set to the proper input value prior to using cpuid. The retrieved information using cpuid is returned in the eax, ebx, ecx, and edx registers. The _CPUID$ value is obtained by setting eax = 0 before invoking cpuid. The CPU stores the twelve-character ASCII string in ebx, edx, ecx (in that order), which is then copied to _CPUID$. The value stored in eax is ignored. The 32-bit integer global variables _CPUID and _CPUIDD return information when the input parameter eax = 1. The return value in eax specifies the signature of the CPU and is stored in _CPUID. The return value in edx specifies the feature flags and is stored in _CPUIDD.
See Also
{Created by Sjouke Hamstra; Last updated: 20/11/2021 by James Gaite}